Layer Stack#

qpdk.tech.LAYER_STACK gives each GDS layer a material, a thickness and a height zmin. Field solvers and 3D views extrude the layout from it. The figure below shows every level of every stack. The main cross-section is LAYER_STACK_FLIP_CHIP_BACKSIDE, which holds the base stack, the flip-chip top chip and the backside metal of both chips, with heights measured from the top of the bottom silicon substrate. The panel on the right shows the gatemon films.

MB_ETCH (3/1) slots Substrate: Si, 𝜀 r = 1 1 . 4 5 M1_ETCH (1/1) slots M2_ETCH (2/1) MB2_ETCH (4/1) slots 𝑧 = 0 200 nm −500 µm −500.2 µm 10 µm 10.2 µm 510.2 µm 510.4 µm Vacuum 10 1 2 3 4 5 6 7 8 9 16 17 14 13 18 15 19 20 Gatemon films 𝑧 = 0 at the oxide surface nanotube (not extruded) 2 21 22 23 24 25 26 QPDK LAYER STACKS Cross-sections, not to scale. Every level of every stack is numbered and listed below. LAYER_STACK (base process, all stacks) 1 M1_ground Nb · 200 nm · 𝑧 0 · derived from SIM_AREA 2 M1 Nb · 200 nm · 𝑧 0 · M1_DRAW (1/0) 3 Airbridge_Via Nb · 100 nm · 𝑧 200 nm · AB_VIA (10/1) 4 Airbridge Nb · 200 nm · 𝑧 300 nm · AB_DRAW (10/0) 5 JosephsonJunction AlOx/Al · 70 nm · 𝑧 0 · JJ_AREA (20/0) 6 NbTiN NbTiN · 15 nm · 𝑧 0 · NbTiN (25/0) 7 IndiumBump In · 10 µm · 𝑧 200 nm · IND (30/0) 8 TSV TiN · 500 µm · 𝑧 −500 µm · TSV (31/0) 9 Substrate Si · 500 µm · 𝑧 −500 µm · SIM_AREA (98/0) 10 Vacuum vacuum · 500 µm · 𝑧 200 nm · SIM_AREA (98/0) 11 VacuumGap_Post Al · 70 nm · 𝑧 200 nm · derived from VG_TOP 12 VacuumGap_Top Al · 120 nm · 𝑧 270 nm · VG_TOP (40/0) LAYER_STACK_FLIP_CHIP adds the top chip 13 M2 Nb · 200 nm · 𝑧 10 µm · M2_DRAW (2/0) 14 M2_ground Nb · 200 nm · 𝑧 10 µm · derived from SIM_AREA 15 Substrate_top Si · 500 µm · 𝑧 10.2 µm · SIM_AREA (98/0) LAYER_STACK_BACKSIDE adds the bottom-chip backside 16 MB Nb · 200 nm · 𝑧 −500.2 µm · derived from SIM_AREA 17 Vacuum_bottom vacuum · 500 µm · 𝑧 −1000.2 µm · SIM_AREA (98/0) LAYER_STACK_FLIP_CHIP_BACKSIDE adds the top-chip backside 18 TSV2 TiN · 500 µm · 𝑧 10.2 µm · TSV2 (32/0) 19 MB2 Nb · 200 nm · 𝑧 510.2 µm · derived from SIM_AREA 20 Vacuum_top vacuum · 500 µm · 𝑧 510.4 µm · SIM_AREA (98/0) LAYER_STACK_GATEMON (standalone; M1 is 155 nm thick here) 21 Oxide SiO 2 · 150 nm · 𝑧 −150 nm · SIM_AREA (98/0) 22 ContactNb Nb · 35 nm · 𝑧 0 · CNT_CONTACT (21/0) 23 ContactAu Au · 10 nm · 𝑧 35 nm · CNT_CONTACT (21/0) 24 hBN hBN · 30 nm (default) · 𝑧 45 nm · HBN (23/0) 25 TopGate Al · 100 nm · 𝑧 75 nm · TOP_GATE (22/0) 26 Reconnection Al · 100 nm · 𝑧 45 nm · JJ_PATCH (20/1)

Notes:

  • M1_ground has no drawn layer of its own. It is derived as SIM_AREA minus M1_ETCH and M1_DRAW, so the solver sees the implicit ground plane around etched slots. M1 is the drawn metal (M1_DRAW).

  • Substrate and Vacuum both extrude SIM_AREA, the simulation region.

  • LAYER_STACK_FLIP_CHIP adds the top chip: M2 (M2_DRAW) and M2_ground (Nb, 200 nm) at z = 10 µm, the indium bump height, and Substrate_top, a second 500 µm silicon substrate above them. M2_ground is derived like M1_ground, from SIM_AREA minus M2_ETCH and M2_DRAW.

  • LAYER_STACK_BACKSIDE adds MB, a 200 nm Nb backside metal on the bottom face of the substrate at z = −500.2 µm, and Vacuum_bottom, 500 µm of vacuum below it. MB is derived like M1_ground, from SIM_AREA minus MB_ETCH and MB_DRAW, and the TSVs connect it to the front-side M1.

  • LAYER_STACK_FLIP_CHIP_BACKSIDE puts backside metal on both chips. On top of the flip-chip and backside levels it adds TSV2 (TiN, TSV2 layer), running up through Substrate_top from z = 10.2 µm, MB2, a 200 nm Nb film on the top chip’s outer face at z = 510.2 µm, derived like MB from SIM_AREA minus MB2_ETCH and MB2_DRAW, and Vacuum_top, 500 µm of vacuum above it. TSV cells take chip="bottom" or chip="top" to pick M1/MB/TSV or M2/MB2/TSV2, as listed in qpdk.tech.CHIP_LAYERS.

  • LAYER_STACK_GATEMON (get_gatemon_layer_stack()) puts z = 0 at the top of a 150 nm oxide, makes M1 155 nm thick, and adds the contact, hBN, top gate and reconnection films. The hBN thickness is a parameter (30 nm by default) and the top gate sits on it. The nanotube itself is not extruded.

  • LAYER_STACK_3D is the base stack plus the gatemon films, with Reconnection moved to the junction height. It also previews the M2, MB, MB2 and TSV2 faces. Their ground planes and the top chip’s substrate appear only inside the SUBSTRATE (bottom chip) and SUBSTRATE_TOP (top chip) die footprints, so they do not appear under every layout. Both substrates are marked translucent with info["opacity"].

  • The material properties, such as relative permittivity and loss tangent, are in qpdk.tech.material_properties.