ubcpdk.components.via_stack_heater_mtop

ubcpdk.components.via_stack_heater_mtop(*, size=(10, 10), layers: tuple[LayerSpec | None, ...] = ((11, 0), (12, 0)), layer_offsets: Floats | None = None, vias: tuple[ComponentSpec | None, ...] | None = (None, None), layer_port: LayerSpec | None = None, correct_size: bool = True, slot_horizontal: bool = False, slot_vertical: bool = False) → Component

Rectangular via array stack.

You can use it to connect different metal layers or metals to silicon. You can use the naming convention via_stack_layerSource_layerDestination contains 4 ports (e1, e2, e3, e4)

also know as Via array http://www.vlsi-expert.com/2017/12/vias.html

spacing = via.info[‘spacing’] enclosure = via.info[‘enclosure’]

Parameters:

• size – of the layers.

• layers – layers on which to draw rectangles.

• layer_offsets – Optional offsets for each layer with respect to size. positive grows, negative shrinks the size.

• vias – vias to use to fill the rectangles.

• layer_port – if None assumes port is on the last layer.

• correct_size – if True, if the specified dimensions are too small it increases them to the minimum possible to fit a via.

• slot_horizontal – if True, then vias are horizontal.

• slot_vertical – if True, then vias are vertical.